1. Field of the Invention
The present application relates to die placement on a semiconductor wafer, and more particularly to selecting a die placement to reduce test time of the dies on the semiconductor wafer.
2. Related Art
Semiconductor devices are typically manufactured by fabricating the devices on a semiconductor wafer. An individual device is formed as a die on the wafer using known semiconductor fabrication processes. Depending on the size of the die, a single wafer can contain hundreds of dies. The dies are generally arranged in a pattern (i.e., a die placement) on the wafer to maximize the number of dies on the wafer.
After the devices are fabricated on the wafer, the devices are electrically tested. The cost of testing can contribute to 30 percent and more of the overall cost of the devices. Semiconductor manufacturers are increasingly performing comprehensive testing of dies, meaning that each die is tested, while the dies are still on the wafer. This process enables the manufacturers to track the locations of the dies that fail or have low yield. However, performing comprehensive testing of dies increases the overall test time.
In one approach to reducing the amount of time needed to test the dies on a wafer, the tester used to test the dies is modified. In particular, the tester head is modified to adjust to a particular die placement. Modifying the tester head, however, can be difficult and expensive.